This invention relates to data processing apparatus. More specifically, the invention is concerned with a pipelined data processor, in which each instruction passes through a sequence of processing stages which perform successive stages of execution of the instruction.
It is well known to provide checking facilities for monitoring the operation of a data processor, to detect failures such as hardware faults or software errors. For example, parity checking may be used to detect hardware faults. When a failure is detected, a signal sometimes referred to as a "Help" signal may be generated, requesting assistance from a diagnostic processor. When it receives the Help signal, the diagnostic processor stops the rest of the system and initiates diagnostic action to determine the cause of the failure.
The object of the present invention is to provide an improved error handling arrangement for a pipelined data processor.